TS EAMCET 04 May 2019 Shift 2 Solved Paper

Consider the circuit diagram shown below.
When the terminal A and B are at low, then 5V of supplu from input appears across resistor R in opposite sense of voltage V2 which eliminates the voltage across R. Therefore, the final output across R is zero.
When both terminal of A and B is at high then the diodes becomes revere bias.
The situation is obtained only is AND gate. Hence, the output Q will act as AND gate.