GATE Electronics and Communications (EC) 2019 Solved Paper

A standard CMOS inverter is designed with equal rise and fall times $\left({\mathit{\beta }}_{\mathit{n}}={\mathit{\beta }}_{\mathit{p}}\right)$. If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NML) and the HIGH noise margin ${\mathit{N}\mathit{M}}_{\mathit{H}}$ ? A. N ${\mathit{M}}_{\mathit{L}}$ increases and $\mathit{N}{\mathit{M}}_{\mathit{H}}$ decreases. B. Both $\mathit{N}{\mathit{M}}_{\mathit{L}}$ and $\mathit{N}{\mathit{M}}_{\mathit{H}}$ increase. C. $\mathit{N}{\mathit{M}}_{\mathit{L}}$ decreases and $\mathit{N}{\mathit{M}}_{\mathit{H}}$ increase. D. No change in the noise margins.