GATE Electronics and Communications (EC) 2019 Solved Paper

let output of NAND gate is $\mathit{M}$ and output of NOR gate is $\mathit{N}$
$\therefore \mathit{M}=\overline{{\mathit{E}}_{\mathit{N}}\cdot \mathit{D}}$
And $\mathit{N}=\overline{{\overline{\mathit{E}}}_{\mathit{N}}}+\mathit{D}$
$\therefore \mathit{N}={\mathit{E}}_{\mathit{N}}\cdot \overline{\mathit{D}}$
When ${\mathit{E}}_{\mathit{N}}=0$
$\mathit{M}=1$ and $\mathit{N}=0$
So both PMOS and NMOS will be OFF
So $\mathit{F}$ will be at high impedance
When ${\mathit{E}}_{\mathit{N}}=1$

So this CMOS will act as not gate
$\therefore$ Option $\left(\mathit{A}\right)$ is correct.