GATE Electronics and Communications (EC) 2016 Shift 1 Solved Paper

The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-𝑁 counter (comprising ÷ 2 ,÷ 4, ÷ 8, ÷ 16 outputs) is sketched below. The synthesizer is excited with a 5 kHz signal (Input 1). The free-running frequency of the PLL is set to 20 kHz. Assume that the commutator switch makes contacts repeatedly in the order 1-2-3-4.

The corresponding frequencies synthesized are: