A 1 to 8 demultiplexer with data input D in , address inputs S 0 , S 1 , and S 2 , (with S 0 as the LSB) and Y̅ 0 to Y̅ 7 as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A 0 and A 1 ) as shown in the figure. D in , S 0 , S 1 , and S 2 are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be

Correct Answer is : Din, S2, S0, and S1

GATE Electronics and Communications (EC) 2015 Shift 2 Solved Paper

Question : 48 of 65

Marks: +1, -0

A 1 to 8 demultiplexer with data input D_in, address inputs S₀, S₁, and S₂, (with S₀ as the LSB) and Y̅₀ to Y̅ ₇ as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A₀ and A₁) as shown in the figure. D_in, S₀, S₁, and S₂ are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be

S2, Din, S0, and S1
S1, Din, S0, and S2
Din, S0, S1, and S2
Din, S2, S0, and S1

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