GATE Electrical Engineering (EE) 2019 Solved Paper

Question : 33 of 65

Marks: +1, -0

Given,

V_{85}

is the gate-source voltage,

V_{d s}

is the drain source voltage, and

V_{\;\text "th "\;}

is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are

${V}_{ {gs}}> {V}_{ {th}} ; {V}_{ {ds}} ≥ {V}_{ {gs}}- {V}_{ {th}}$
${V}_{ {gs}}< {V}_{\;\text "th "\;} ; {V}_{ {ds}} ≤ {V}_{ {gs}}- {V}_{\;\text "th "\;}$
${V}_{ {gs}}< {V}_{ {th}} ; {V}_{ {ds}} ≥ {V}_{ {g}}- {V}_{ {th}}$
${V}_{ {gs}}> {V}_{ {th}} ; {V}_{ {ds}} ≤ {V}_{ {gs}}- {V}_{ {th}}$

Solution:

For saturation region

{V}_{ {ds}} ≥ {V}_{ {ds}}

(sat),

{V}_{ {ds}}

(sat)

= {V}_{ {gs}}- {V}_{ {th}}

∴ {V}_{ {ds}} ≥ {V}_{ {gs}}- {V}_{ {th}}

and

{V}_{ {gs}}> {V}_{ {th}}

Go to Question:

Prev Question

Next Question