GATE Computer Science (CS) 2019 Solved Papers

Question : 11 of 65

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A certain processor uses a fully associative cache of size 16 kB. The cache block size is16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

24 bits and 0 bit
28 bits and 4 bits
24 bits and 4 bits
28 bits and 0 bits

Validate

Solution:

Cache memory size = 16 kB
Block size = 16 B
Main memory address = 32 bit
Number of lines (N)

=\;{16 {K}}/{16} ⇒ \;{2^{14}}/{2^{4}}=2^{10}

Fully associative cache memory (N-way)

=\;{ {N}}/{ {P}-\;\text " way "\;} ⇒ \;{2^{10}}/{2^{10}}=1

So, number of sets (S)

∴ Address format:
So, TAG = 28 bit
Index = 0 bit (No address)

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