GATE Computer Science (CS) 2018 Shift 1 Solved Paper

Question : 40 of 65

Marks: +1, -0

The size of the physical address space of a processor is

2^{p}

bytes. The word length is

2^{W}

bytes. The capacity of cache memory is

2^{N}

bytes, The size of each cache block is

2^{M}

words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is

Solution:

MM space

=2^{P}

bytes
Pysical Address (PA) size = P bits
CM size

=2^{N}

bytes
Block size

=2^{M}

words

=2^{M}

words

* 2^{w}

bytes\/word

=2^{(M+W)}

bytes
Number of lines

=\;{\;\text " CM size "\;}/{\;\text " Block size "\;} ⇒ \;{2^{N}}/{2^{M+W}}

⇒ 2^{N-M-w}

Number of sets

=\;{\;\text " Number in "\; {cm}}/{\;\text " P-way "\;}

=\;{2^{N-M-W}}/{K}

The Address format

⇒( {N}- {M}- {W}-\log _{2} {K})

∴

Tag size

⇒ {P}-( {M}+ {W}-\log _{2} {K}+ {M}+ {W})

⇒ {P}- {N}+\log _{2} {K}

Go to Question:

Prev Question

Next Question