GATE Computer Science (CS) 2018 Shift 1 Solved Paper
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A 32 -bit wide main memory unit with a capacity of is built using -bit DRAM chips. The number of rows of memory cells in the DRAM chip is . The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read\/write operations in the main memory unit is
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