GATE Computer Science (CS) 2017 Shift 2 Solved Paper

In a two-level cache system, the access times of L₁ and L₂ caches are 1 and 8 clock cycles, respectively. The miss penalty from the L₂ cache to main memory is 18 clock cycles. The miss rate of L₁ cache is twice that of L₂. The average memory access time (AMAT) of this cache system is 2 cycle. The miss rates of L₁ and L­₂ respectively are: