GATE Computer Science (CS) 2017 Shift 1 Solved Paper

Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:
i) a naïve pipeline implementation (NP) with 5 stages and
ii) an efficient pipeline (ER) where the OF stage is divided into stages OF1 and OF2 with execution times of 12ns and 8ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards in _______.