GATE Computer Science (CS) 2017 Shift 1 Solved Paper

Consider a two-level cache hierarchy with L1 and L2 cashes. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1: the L2 cache experiences. On average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ________.